Today, typical computer systems include a microprocessor for executing instructions, a memory for storing instructions and data and a bus for communicating information. Some current microprocessors perform pipelined execution of instructions. In a pipelined processor, the entire process of executing instructions is divided into stages of execution, during which a separate part of the execution process is completed. By pipelining, portions of many instructions are at different stages of execution, such that every cycle another instruction completes execution. By completing execution of an instruction each clock cycle, the throughput of the microprocessor increases.
In computer systems, microprocessors are widely involved in the transfer of data between themselves and other components in the computer system. The data is transferred between separate components (e.g., a microprocessor and main memory) over a data bus. Transfers usually occur in single data cycles. A single data cycle typically includes two clock pulses. During the first clock pulse, an address is transferred onto the address bus, while during the second clock phase, the data corresponding to the address is transferred onto the data bus.
A typical data transfer cycle involving a microprocessor in a computer system is shown in FIG. 1. Referring to FIG. 1, the data transfer begins with the microprocessor driving an address, ADDR1, onto the address bus (A31-0). An address strobe signal, ADS#, is asserted by the microprocessor to indicate that a bus cycle is occurring and that the address currently on the address bus is valid. The address is then decoded in the computer system. The data, DATA 1, is then driven onto the data bus. In current computer systems, the data usually comprises four bytes. A ready signal, RDY#, is asserted when the data on the data bus is valid and is ready to be transferred. (The # indicates that the signal is active low).
One problem with the transfer depicted in FIG. 1 is that another address cannot be driven onto the address bus until after the data has been transferred. In other words, before the next address can be strobed (e.g., ADDR2 in FIG. 1), the data must have been transferred (e.g., DATA1 in FIG. 1). Therefore, there is an inherent latency between the time the address is strobed and decoded until the time the data is actually transferred. However, while the actual transfer of data occurs, the address decoders are not functioning. It would be desirable to have the next address strobed and decoded while the data corresponding to the current address is being transferred. In this manner, data can be transferred every clock cycle. Address pipelining is implemented in the Intel 80386 brand of microprocessor sold by the assignee of the present invention which does not perform burst cycles.
For bus requests that required more than a single data cycle, many microprocessors can accept burst cycles instead of normal cycles. A burst cycle transfers multiple bytes of data across the bus during one long memory cycle. For example, a transfer of a 128-bit data item across a 32-bit bus would normally occur in four groups, each group containing 4 bytes. The initial address (e.g., the first byte) is used by the processor to compute the remaining addresses for the subsequent data bytes. The concept of burst cycle transfers is well-known in the field. Note that the problem described above associated with single data cycle transfers is also applicable to burst cycle transfers in that the address corresponding to the next burst cycle cannot be asserted until the last byte of data corresponding to the first burst cycle has been transferred.
It is possible that a microprocessor may be coupled to some devices which require burst transfers and some devices which require non-burst transfers. In this type of system, it would be desirable to have the microprocessor determine automatically the type of transfer (i.e., burst or non-burst) before performing the transfer, such that the microprocessor could accommodate multiple data transfer types (i.e., burst and non-burst).
As will be shown, the present invention provides a method and means for allowing the next address to be strobed and decoded while the data corresponding to the current address is being transferred. To facilitate this, the present invention provides a method and means for pipelining address in a microprocessor. The present invention also provides a method and means for determining the type of transfer being performed (e.g., burst vs. non-burst). In this manner, the present invention is able to pipeline burst addresses and pipeline non-burst address so that the throughput of data transfers between the microprocessor and the remainder of the computer system is increased.